1. Field of the Invention
The present invention relates to a method of aligning wafers, and more particularly, to a method which utilizes a signal of an alignment mark captured from a reticle by a reticle alignment system (RAS) as standard signals to calibrate a pre-layer wafer alignment mark captured by a wafer alignment system (WAS), and further filters unnecessary bias resulting from process errors.
2. Description of the Prior Art
In the manufacturing process of integrated circuits (IC), the lithography process is one of the most important technologies. The quality of the lithography process is evaluated by critical dimension (CD) and alignment accuracy (AA). Besides the performance of the alignment system and the accuracy of metrology, the alignment mark (AM) on the wafer is another factor that affects the alignment accuracy. Circuit accuracy is profoundly affected by the AM, especially when process error happens. Therefore, to design an alignment system that can eliminate the bias through capturing and comparing signals, and moreover to calibrate the biased AM so that the influence of process error can be reduced to a minimum, is an urgent topic for study.
According to operation mode of the wafer alignment systems in the prior art, two common operation systems exist: steppers and scanners. Both the steppers and the scanners utilize the reticle alignment system (RAS) and the wafer alignment system (WAS). Please refer to FIG. 1. FIG. 1 is an operation flow chart of an RAS in the prior art. As shown in FIG. 1, the operation procedure of an RAS in the prior art starts by a start step 100 for installing a reticle to be exposed into a reticle alignment machine (RAM). Then, an interferometer-reset step 102 is performed to reset an interferometer of the RAM, and a stage set step 104 is performed with a field image alignment sensor (FIA sensor).
A reticle load step 106 is performed to load the reticle, and a reticle search alignment step 108 is performed with a video reticle alignment sensor (VRA sensor) to adjust the coordinates of the reticle by rotating the reticle. Then a reticle biased-angle determination step 110 is performed; if the reticle biased-angle is too large, the reticle is removed by a robot arm and rotated to reload, as step 112 and 114 show in FIG. 1. Afterward, a fine alignment step 116 is performed by utilizing a set of alignment marks (AM) of the reticle, and a reticle interferometer calibration step 118 is performed with the VRA sensor.
A reticle rotation compensation step 120 is performed by rotating the reticle. After that, two simultaneous baseline check (simultaneous BCHK) steps 122 and 124 are performed respectively with the FIA sensor and a laser interferometric alignment sensor (LIA sensor) by employing 6 sets of AMs of the reticle to simultaneously fine adjust the corresponding coordinates of the reticle to a baseline of the steppers or the scanners. Finally, a non-simultaneous BCHK step 126 is performed with a laser step alignment sensor (LSA sensor) to accomplish the operation of the RAS of the prior art.
Please refer to FIG. 2. FIG. 2 is an operation flow chart of a WAS in the prior art. As shown in FIG. 2, the operation procedure of a WAS in the prior art starts with a start step 200; a wafer having a pre-layer AM is installed in an RAM. Primarily, a pre-alignment step 202 is performed to align the wafer approximately. Then a first wafer alignment step 204 is performed, a search alignment step 206 is performed with a FIA or a LSA sensor, and a rotation calibration step 208 is performed. If the required rotation angle exceeds 500 micro radians, repeat the pre-alignment step 202; if not, continue performing a second wafer alignment step 210. Thereafter an enhanced global alignment (EGA) step is performed: performing a fine alignment step 212 with the FIA, the LSA, or a LSA sensor to align the wafer with the reticle and calculate the corresponding coordinates of the reticle and the wafer to the baseline so that the coordinates of the reticle and the wafer are on the same baseline; and performing a wafer exposure step 214 to transfer layouts of the circuit pattern of the reticle onto the wafer for accomplishing an overlay procedure in the prior art.
The alignment mark plays an important role in the operation of an RAS. All the above-mentioned FIA, LSA, and LIA sensors are applied to capturing the AM and transferring signals. With the progress of RAM, when errors are already negligible, the quality of lithography process is affected profoundly by the accuracy of AM capturing. However, when the AM is transferred from a precedent process onto the wafer, some inevitable process errors could occur, such as changes of temperature, time, and pressure that reduce the surface uniformity of wafer, or over polishing in the chemical mechanical polishing (CMP) process that cause the distortion of the AM. Because the exposure process is performed when the current layer is aligned with the AM of the precedent layer, the patterns of different layers are overlaid. Images and signals captured and transferred by the FIA, LSA, and LIA would be weakened or biased by inevitable process errors.
Please refer to FIG. 3(a) and FIG. 3(b). FIG. 3(a) is a schematic diagram of normal AM signals captured and transferred by the FIA, LSA, and LIA sensors. FIG. 3(b) is a schematic diagram of biased AM signals captured and transferred by the FIA, LSA, and LIA sensors. As shown in FIG. 3(b), when the AM is damaged because of process errors, signals generated by the AM would derive unnecessary bias that is different from signals generated by a normal AM. The biased signals would affect the reliability and precision of the search alignment step 206 and the fine alignment step 212, and further affect the overlay result of lithography process. Therefore to design a wafer alignment method unaffected by process errors is an important topic for study in the semiconductor manufacturing process.